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frequency divider 分頻器。

frequency meter

One is based on vco , and the other is based on frequency divider . the advantages and disadvantages of them are discussed in the thesis . furthermore , a method of realizing dead time changeable circuit is given , which makes the designed driving circuit have more latitude when it is used 此外,論文還設計了兩種驅動信號產生電路,一種基于vco ,另一種基于振蕩器和分頻器,并對比了兩者的優缺點;給出了一種死區時間可變的電路實現方案,使所設計的驅動電路使用時具有更大的靈活性。

In the sub block circuit design , the contents that the author had introduced include : the principle of band gap voltage reference and the design technique in low power supply ; the analysis of spike pulse noise rejection , frequency divider and dead time in oscillator and control circuit ; the selection of the width and length ratio of four switches and 2x / 1x mode change point in driver and mode selection circuits 在子電路設計中,作者比較深入分析的內容有:基準電路的原理及低電源電壓下基準電路的設計;振蕩器和控制電路中尖峰脈沖噪聲抑制、兩分頻電路及死區時間設定;驅動及模式選擇電路中開關管的寬長比的選擇及模式轉換點的設計。

This paper introduces the principle of the frequency division and presents the circuit design of the decimal frequency divider based on fpga . the vhdl language is used for the programming 摘要介紹了一種基于fpga的小數分頻器的分頻原理及電路設計,并用vhdl進行編程實現,并對這種小數分頻器的抖動進行分析和計算。

The pll consists of a crystal oscillator , a ring voltage - control - oscillator , a frequency divider , a phase / frequency detector , a charge pump and a loop filter 設計的電路包括20mhz晶體振蕩器,鑒頻鑒相器,壓控振蕩器,固定分頻器,電荷泵和低通濾波器。

Design of hardware consists of three pll loops , micro wave sample mixer , fractional - n frequency divider 硬件電路包括三個鎖相環,取樣混頻器,分數分頻器的設計等。

Variable division frequency divider 可變分頻器

N is the desired noninteger frequency divider N為所要求的非整數分頻值。